The Design And Realization Of Orthogonal STBC Based On FPGA

With the rapid development of wireless mobile communication technology, single voice and text communication services has become unable to meet the needs of the people. That requires higher transfer rate, channel capacity and reliability of the communication system. However, on the basis of information theory these requirements are contradictory to channel spectrum utilization. In addition, due to the interference with the multipath propagation of the wireless channel and other factors, it is still difficult to make the communication system satisfactory.MIMO (Multiple Input Multiple Output, MIMO) system is widely studied as an effective way to improve the spectrum utilization and resist multipath fading. MIMO is used to describe the abstract mathematical model of the multi-antenna wireless communication system, which can transmit signals independently at the transmitting end by using multiple antennas and simultaneously receive and recover the original information at the receiving end. STBC (Space Time Block Code), due to the simple structure, decoding and good performance of resistance to fading, has been written in the third generation cellular mobile communication standards and become an integral part of the fourth generation mobile communication standards framework.At the same time, since the time-varying characteristics of the wireless channel environment lead to the different time of the propagation channel inconsistent, it brings the uncertainty to the test of a communication system. Therefore it is particularly important to design channel simulator in the lab experiment.In this paper, the STBC technology of MIMO system and the hardware implementation of wireless channel have been studied.Firstly, the paper describes the characteristics and classification of wireless fading channel and analyses modeling methods of multiple, independent identically distributed flat Rayleigh fading channel. Based on Jakes model, it puts forward using FPGA (Field Programmable Gate Array) to realize the scheme of channel simulator and gives simulation results.Secondly, the principle, techniques and the performance of coding and decoding are analyzed and the STBC hardware implementation scheme is designed based on FPGA. Three different demodulation modes in QPSK,8PSK and16QAM are used to deduce the implementation algorithm based on FPGA in detail aiming at two coding schemes of STBC-G2and H3. Meanwhile, we optimize the decoding algorithm to reduce its complexity.Finally, through the combination of the channel simulator based on FPGA and the codec of STBC, a complete and equivalent low pass communication system is constructed. On ModelSim platform, the system performance is tested. In addition, the system is simulated theoretically under the same conditions. The results show that the performance of the system based on FPGA agrees well with theory, so as to verify the effectiveness and accuracy of the implemented system.