The Radar Super-resolution Processing Technology

Radar target azimuth information is obtained by the antenna beam scanning, the radar antenna azimuth resolution depends on the horizontal beam width, if it is a narrow beam, you can get high resolution. Therefore, under normal circumstances are taken to increase the antenna aperture radar transmit frequency and improving methods. Therefore Super-resolution processing using radar technology can be further improved with limited resources radar azimuth resolution.To effectively improve the non-coherent pulse radar resolution of the problem, the paper solve this problem first studied the radar antenna pattern functions, objectives and other mathematical models; then studied to improve radar resolution commonly used wavelet transform, Wiener inverse filtering and limiting the iterative algorithm, but also for the impact of noise on improving radar resolution, as well as two radar echoes with aliasing when radar echoes can not be resolved problem, a Wiener inverse filtering and restrictions iterative deconvolution improved algorithm, and the simulation experiment analysis through a variety of algorithms to improve radar resolution, comprehensive research on hybrid deconvolution algorithm to improve the resolution of the radar, and the simulation experiment analysis, proved that the improved hybrid anti-convolution algorithm to improve the effectiveness of the radar resolution, this method not only can reduce the amount of calculation algorithms, and can effectively suppress noise and reduce false peaks.This topic using FPGA super-resolution processing to ensure that the super-resolution processing in real time. ISE10.1using Xilinx’s software processes the entire system the overall design of the FPGA, in turn, the algorithm in FPGA simulation experiment is divided into three parts, including FPGA-based data storage and FPGA-based FFT, also the body portion including a software algorithm implementation. Finally on the programming process using MATLAB simulation results verify the feasibility of a comparison, results of this algorithm can not only reduce the amount of computation, but also suppress noise artifact peaks super-resolution processing FPGA implementation.