Research On FPGA Fast Implementation Method Of Super-resolution Imaging

Forward looking super resolution radar has wide application space and value in the fields of precise guidance,flight detection and material airdrop.But super resolution images are generally low in resolution and computation big.Therefore,it is of great significance to carry out super resolution processing based on FPGA for real-time radar imaging.In this paper,for the super resolution imaging of forward-looking scanning radar,total variation super resolution imaging processing algorithm is studied.The FPGA architecture signal processor of super resolution imaging is designed,and the transplantation and system design of total variation super resolution algorithm are completed.The specific work content is as follows:(1)According to the spatial motion configuration of the forward-looking scanning radar,derivation of point target distance history,establishing the echo model of the imaging scene.The convolution model of azimuth direction is determined by echo preprocessing.Under the condition of regularization constraints,the gradient information of the target is introduced.The total variation super resolution imaging algorithm is derived,and the theoretical simulation and the measured data are processed.(2)According to the requirements of the signal processor of total variation super resolution radar,the hardware structure of the super resolution imaging system,the echo acquisition board,the data processing board and the data transmission backboard,as well as the important circuits such as gigabit Ethernet,high-speed communication interface and clock are designed.Data acquisition and storage,SRIO inter-board data transmission and echo signal preprocessing program design are completed(3)For a large number of matrix operations involved in the total variation super resolution algorithm,the structure of matrix pulsating array multiplier is designed.For the iterative calculation in the super resolution algorithm,the data processing board array and pipeline are designed.The above two realize the acceleration of the hardware circuit.(4)The hardware interface,preprocessing module and super-resolution algorithm are debugged for the designed super-resolution FPGA imaging system.Super resolution imaging results are tested and verified using field real scene data.