ASIC Design And Implementation Of MuItithread Pipline Processor For IP Packet Processing

Since network users and data traffic increase exponentially, faster networkprocessing and wider bandwidth are needed. As a programmable ASIC processor,network processor not only provides the system with high performance ASIC-likeprocessing speed but also proffers similar flexibility of general-purpose processor.Therefore, it meets the high-performance requirements of many applications.As the most important design unit of network processor, the multithread piplineprocessor is used to complete checksums of data packets, header processing andclassification, routing table lookup and forwarding, package storing in the storage unit,header modification and forwarding packets to the correct port, etc. Therefore, theprocessor’s design largely determines the network processor’s performance, and thefrequency of the multithread pipline processor directly affects the level of operatingfrequency, throughput and performance of entire design platform。In this paper, the multithread pipline processor’s design and implementation havebeen done: Firstly, the multithread pipline processor’s instruction set and5-stagepipeline structure are introduced. In order to implement complicated network packetsprocessing, comparing with general instruction set, the multithread pipline processor,in order to complete complicated network packets processing, adds external referenceinstruction and ALU_SHF instruction，which are for data accessing and calculating;forwarding logic is adopted to deal with the data hazard; the branch prediction anddefer slots are used to deal with the control hazard. Secondly, the ASICImplementation of the multithread pipline processor based on SMIC0.13μm processhas been done. This paper introduces a series of problems of conversion from FPGAdesign to ASIC design, and then, gives the solutions to these problems at first. Then,the multithread pipline processor and arbiter’s synthesis process are introduced fromdesign constraints, synthesis tool’s optimization and design optimization. This papermainly focuses on optimizing the design to slove the timing violations. The targetoperating frequency of the multithread pipline processor is232MHz in a0.13-microntechnology. After optimization work, the data transmitting processor’s maximumoperating frequency is300MHz. Finally, the multithread pipline processor’s physicaldesign and implementation are finished based on the netlist and constraints file.