A Dynamic Priority Algorithm For Network On Chip Switches

Network on chip is a new multi-cores interconnect technology, which separates data processing elements and communication resources and has good parallel communication skill and scalability. It uses global asynchronous locally synchronous technology in order to solve a single clock problem of system on chip. Routing node is the basis of information exchange between IP cores and the significant part of network on chip, so high-performance routing is the key to high-performance network on chip. Switches architecture and scheduling algorithm are important parts of the routing node and their performances directly affect the performances of the routing node.This paper firstly describes switches architecture which bases on queuing mechanisms. Input queuing is becoming the mainstream architecture of switch architecture because that it has no requirement of speedup and overcomes the shortage of HOL by using virtual output queuing technology. Then, the performances of input queuing scheduling algorithms are discussed. Finally, A dynamic priority scheduling algorithm which bases on input queuing switch and provides "Quality of Serve" guarantee is proposed. It has universal applicability and can be applied no matter what facts determine priority. The priority can be dynamically changed in each time slot and avoid low priority starving. In addition, the simulation platform is designed and the results showed that iDP was better than Iterative Round Robin Matching with Slip when iteration times were two in four traffic models.