Based On Two-dimensional Image Compression Decompression Design Of The Algorithm

With the development of internet TV, smart TV and cloud TV, the requirements of chip performance and cost for video processing soc is increasing. In the video processing chip, the image compression technology is good for performance and cost. It can increase memory bandwidth and reduce the memory resources. Increasing the image compression ratio is very good for video processing chip on the premise of ensuring image quality. In the company products, using the one-dimensional image compression algorithm, the compression ratio is only1.56. Therefore, two-dimensional image compression algorithm is used for the purpose of improving the image compression ratio. By using two-dimensional image compression algorithm, the compression ratio can be increased to2.5.The two-dimensional image compression algorithm and the decompression design are analyzed in the thesis.Decompression design is achieved through the following aspects. The first is the system block diagram design. Combining with the application requirements of the algorithm in the system, decompression hardware implementation is feasible. The second is describing the decompression design codes with Verilog HDL language and completing functional simulation. The third is using Design Compiler to synthesize codes and analyze timing. The fourth is to verify the logical equivalence of the design codes and the synthetical netlist. The fifth is using Static timing analysis tool to verify the timing is consistent with the design requirements. Finaly, FPGA verification is completed for the decompression design.From the simulation results, timing analysis and FPGA verification, the decompression design results are consistent with the two-dimensional image compression algorithm results and meet the timing requirements of the system.