Design Of Grating Nano-Scale Subdivision IP Core Based On FPGA

Nano-scale displacement measurement is the main development direction of precisedisplacement measurement technique in the21st century, at a central pisition of precisedisplacement measurement field. Grating displacement measurement method is a vitalcomponent of precise displacement measurement, so research of nano-scale gratingdisplacement measurement technology has prominent significance. Aiming at the problemsof low measurement accuracy, long development cycle and high equipment costs inordinary grating displacement measurement system, the paper presents a design of gratingsubdivision IP core which can be applied in nano-scale displacement measurement. Thedesign studies grating Moiré fringe as the research object directly to avoid theconstant-amplitude demand of grating output signals in traditional grating subdivisionmethod, which contributes to the realization of nano-scale grating subdivision.The paper first introduces the progress of nano-scale displacement measurementtechnology and the working principles of grating displacement measurement technology,studies and contrasts the existing grating subdivision methods, determines to utilize CCDMoiré fringe subdivision method as the implementation method of grating nano-scalesubdivision IP core. The paper uses ApGoertzel algorithm and CORDIC algorithm as therealization algorithms of CCD Moiré fringe subdivision, presents the working principles ofthe algorithms, analyzes and simulates the Moiré fringe subdivision effects with MATLAB,which verifies the feasibility and rationality of algorithms.FPGA is used for specific design of grating subdivision IP core. IP core is analyzedwith modular structure aiming at the actual function and internal data processing flow,which is divided into three parts: spectrum analysis module, phase conversion module, anddisplacement calculation module. The paper describes the design method of each moduleand the top-level intergration processing detailedly, utilizes Quartus II for static timinganalysis of IP core, and utilizes Modelsim SE for function test of each module and thewhole design. Analysis and simulation results show the subdivision IP core based on FPGA technique can meet the requirements of grating nano-scale displacement measurement. Thepaper also designs CCD image sensor circuit and CCD signal processing circuit, utilizesFPGA as the controller to generate driving signals and configuration signals of circuit.Grating nano-scale subdivision IP core has the advantages of high subdivision timesand strong stability, which can conduct nano-scale grating subdivision and achievenano-scale displacement measurement with20um pitch grating. Besides, IP core has thecharacteristics of high reliability, strong modifiability and reusability, which has a certainpractical significance.