The Design And Research Of DCM In FPGA

With the development of programmable logic devices, on-chip clock signal, thesystem clock frequency demand and others in the area of programmable logic devicesshowed the increasing demands.Theclock management module in the programmablelogic device becomes increasingly important. The rapid development of foreignprogrammable logic devices, the clock management module is fully functional, XilinxInc., for example, his company’s programmable logic devices designed a clockmanagement module from nothing. First is a DLL module, DCM module, developed toCMT module, so far, the company’s programmable logic devices have been developedto Virtex7series, the clock management module has basically existed in the chip, whichgreatly facilitates the use of the system board level. The programmable logic devicedevelopment in china has a long way to go.Theclock management module is used ashard IP, the module’s performance directly affects the performance of programmablelogic devices.The content of the paper depend on the high density programmable logic products.The clock management module DCM is the main object of study, in-depth analysis ofthe theory of clock management module.One of the main functions of clock skew,frequency synthesizer, digital phase shift, digital spread spectrum arediscussed andresearched in detail, as well as DCM applicationin the FPGA. Basic content asfollows:1. The project as a VLSI design, using a dedicated process in CMST company. Thedesign process first proposed the architecture of the programmable logic device; thenensure the correctness of the functions of the various functional modules of the wholecircuit; the ensure that it meets the performance characteristicsof various functionalmodules by selecting the appropriate process line; Designtop-level architecture top-levelcircuit and draw the top-level layoutin accordance withthe pre-designedstructures;finally do the full circuit functions, performance verification and the layoutof thetop-level verification, to ensure consistency between circuit and layout.2. The research of clock deskew function module,researches the main functional modules DLL which realize the function of clock deskew function, most simple DLLcomprises variable delay chain and the control logic circuit. The input port of the clocksignal driving the delay line, each delay cell represents a different delay. The controllogic circuit includes a phase detector circuit, and a delay chain selection circuit. Bycomparing the input clock edge and the edge of the feedback clock to achieve thedetection DCM locked state. Through simulation analysis, showed that the developedcontent meets the requirements of the Data Sheet.3. ResearchesFrequency synthesizer module, describesmodule’scharacteristics ofthe operating frequency range and AC，which is compatible with the original modelbutthe value is different. Module provides CLK2X which doubles the input clockfrequency and CLK2X180which negates signal CLK2X180.4. Researches the digital phase shift function,providesthe proposed coarseadjustment and fine adjustment of the clock phase shift. In the case of high-frequencyand low-frequency mode, phase shift signal CLK0,CLK90,CLK180,and CLK270providethe preliminary adjustment relative to the input clock with a quarter of a cycle.in accordance with the inherent TAP value, make comparison of the output clock signaland the input clock signal, to achieve the fine phase shift adjustment.5. DCM module’s application in the FPGA, illustratesthe main application of theDCM in the FPGA, simulation analysis withcode.TheconfirmedDCM design isable towork properly in the FPGA full circuit.