Low Power Design And Implementation For Passsive UHF RFID Tag Baseband Processor

RFID (Radio Frequency Identification) is a technology that incorporates the use ofelectromagnetic or electrostatic coupling in the radio frequency (RF) portion of theelectromagnetic spectrum to uniquely identify an object. The passive UHF(Ultra HighFrequency) Radio frequency identification (RFID) technology has become a keytechnology for its long operation range, large information capability, high data rate andlow cost. With the development of information technology, UHF RFID technology willbe integrated with other technologies and become one of the fundamental technologiesin the future information society. For the application demand of UHF RFID chip, ourresearch mainly focuses on low power architecture design, low power design methodsand physical implication methods, based on ISO/IEC18000-6C international standard.Firstly, the power model corresponding to each component in CMOS circuits inASIC/SOC was introduced and the dynamic and static method for power estimation wassummarized. Then, we analyzed the methods which has been used in the industry to lowpower and explained the focal points in detail.Based on the indices of the RFID Tag, a low power baseband architecture isproposed, and lots of efforts has been done on the power optimization methodsapplicable to RFID Tag design at several design levels, including: the introduction ofthe pipeline work mechanism and the clock gated on the system level, the application oflow power code method, the strategy of power optimization in logic synthesis phase,and realization of low power physical design. With the help of these design method, thepower of the baseband is lowered greatly. Thus the sensitivity of tag has been greatlyimproved, and extended its application scope.