An Adaptive Double Plateaus Histogram Equalization Algorithm For Infrared Image Enhancement And Its Realization On FPGA

As different from visible light imaging, gray levels of infrared image obtained frominfrared imaging are concentrated and therefore the image has low contrast. Histogramequalization or modified histogram equalization such as plateau histogram equalization are themost frequently used image enhancement algorithms especially for low contrast and highbackground infrared image. However plateau histogram equalization has the drawback that it isnot adaptable in different application backgrounds. The aim of this paper is to present a newadaptive double plateaus histogram equalization algorithm that can be utilized for variousapplications.In the proposed algorithm, by searching local maximum and by predicting minimum grayinterval, one upper and one lower threshold value are calculated and refreshed in real time; asthe upper threshold is utilized in the algorithm for preventing over enhancement of backgroundnoise with typical gray levels, the lower threshold is also set for protecting detail informationwith fewer pixels from being combined. Therefore, background noise could be constrainedwhile details could be magnified with the two adaptive thresholds.Based upon the proposed algorithm, a creative method of realizing the proposed algorithmon FPGA is also presented. By utilizing parallelism and pipelining technique of FPGA,realization of the algorithm is able to real-timely enhance infrared imaged with high resolutionand high frame rate.Experimental results proved better performance of the proposed algorithm than thetraditional double plateaus histogram equalization, in the three applications such as outdoor longshot, outdoor close shot and indoor shot. Moreover, the proposed algorithm also showedcontrast improvement of2~10dB. Therefore, the proposed adaptive double plateaus histogramequalization algorithm not only can greatly improve infrared image contrast, but also can adaptto various applications; Hardware realization of the proposed algorithm based on FPGA is alsoproved to have very high throughput so that it can be utilized in infrared imaging systems withhigh frame rate and large resolution.