Based On The Clock Regeneration Mechanism Of 6 Channel Led Constant Current Drive Circuit Design

With the intensifying contradiction between energy supply and demand, the LED makes the developed countries compete with each other in this field because of its advantages such as eco-friendly feature, low power consumption, long service life and small volume which all make it the fourth generation green light. Knowing the arrival of the ’blowout’ period of the LED, the major LED driver designing companies have promoted new products frequently to satisfy the present market needs, and also to effectively get the advantages of markets in advance.In this paper, a6-channel constant current LED driver based on the clock regeneration mechanism with programmable PWM outputs has been proposed, which is mainly used for the backlight driver of LCD and decorative LED lighting system. The chip will encompass the clock regeneration mechanism structure,48bits serial shift registers, internal oscillator, control module, PWM gray comparator and output driver stage. The simulation results reveal that the range of the chip’s input voltage is from3.3V to5.5V, and it has3/6channel18mA constant output current, and the matching degree of the output current in the chip is greater than96%, among the chip, however, greater than95%.With the cascade data clock signal’s phase reversed and shape reshaped by the clock regeneration mechanism, the cascade length will have great advantages, and the drive can achieve3or6channel output function at the same time.This paper mainly performs research from the following aspects:1. Based on the research and analysis on the present LED drive circuit, the overall design index and scheme of the chip are proposed with specific functions of every module.2. First we will analyze and explain the meaning of the clock regeneration mechanism in the design. Then we use Cadence to do simulation with related modules, and we use Verilog HDL language to do simulation with8-bit single channel LED driving chip based on clock reverse phase technology, which all prove that this chip can work normally and it has the advantages in the cascade length and it has a3/6 channel selective output function. Eventually we analyze some important circuit module in detail, including the working principle and circuit design. The simulation structure of each module coincides with our goals.3. After the completion of the whole chip design there will be the whole simulation. Then we do tapeout after using CSMC0.5um N-well CMOS process to complete the layout design. Ultimately with the use of the oscilloscope we observe the output waveform of the cascade chip, and analyze that the chip when used in cascade mode will have advantages of remote cascade competence.