FPGA Implementation Of Lossless Compression Encoder And Decoder For Hyperspectral Images

Hyperspectral images contain a mass of spatial information and spectral information of the target area. However, more storage space comes with higher quantity of image information. And the data acquisition of hyperspectral images is very costly. So it is significant to compress the hyperspectral images without damaging the information it contains.In this thesis a lossless compression scheme named optimized combination coding (OCC) is studied, which is a differential prediction-based (DP-based) algorithm for hyperspectral data with very low complexity. FPGA implementation of OCC scheme is presented to satisfy the real-time requirement of the airborne image collection system because of the flexibility, reliability and high speed of FPGA.The thesis focuses on the FPGA implementations of OCC encoder and decoder, by using ISE compilation environment and Verilog HDL. Timing simulation is performed with Modelsim environment. The major works are as follows:(1) With the application of pipeline processing technique, the implementation schemes of OCC encoder and decoder are designed based on FPGA. The compression system is divided into several modules. Each module executes separately and performs parallel.(2) The encoder includes six modules:Prediction module, Difference module, Huffman-coding module, Time-delay module, Width-fix module and Main-control module. The prediction module contains two submodules:predictor1and predictor2. The first five modules are functional modules and perform prediction, difference, Huffman-coding and width-fixing, respectively. These modules are dominated by the Main-control module.(3) The decoder includes four modules:Input&decoding module, Prediction&recovery module, Output module and Control module. The Input&decoding module segments the input data and decodes them. And the decoded data is sent into Prediction&recovery module. In this module image data is recovered through adding the decoded data and predictive value. The Output module gets the recovered data width-fixed and output. Functions, interfaces and process of each module of encoder and decoder are described in detail.(4) Timing simulations and verifications of the designed encoder and decoder are performed based on each functional module. The foundation of Testbench and the generation of excitation signal are presented for every module. The comparison between timing simulation results and predicted results with anticipated outcomes is used to verify whether the modules of the encoder or decoder execute properly. After the description of the difficulties in debugging, the performance of the implementation is analyzed by using the information of clock period and the utilization of logic resources from the generation reports after the implementation.