The Algorithm Implementation And VMM Verification Of Skcore

With the rapid development of IC industry, System-on-chip technology which is Multiplexing of IP cores and ultra-deep sub-micron technology for the support, is the current mainstream of Embedded electronic product design and super LSI. The chip agreement has become increasingly complex, and the scale is getting huge, soc chip usually needs to have a large number of data input and output ports, and transmission of vast amounts of data. Panther series soc chip produced by the United States EXAR Corporation is a high performance, in the case does not affect the computer speed, for massive data processing speed of large software on the market thousands of times. In such a million or even10million gate ASIC design, in order to ensure the success of the project, functional verification consumes about70%of the entire design input, This has become the project’s critical path. How to solve the verification process and validation of quality of the chip has become an urgent task of today’s chip design.Based on the actual projects work of company, In the case of the subsystem of core algorithm processing, which used in PANTHERII project. First described the basis and significance of the functional verification of the development as well as topics, Then described in detail the composition and the basic principles of the SKcore subsystem, specifically addressed several SKcore the building blocks of a PP engine assembly line and demultiplexer, introduces the basic structure of each module and the realization of the principle, illustrates SKcore algorithm is also EXAR company’s patented algorithms--LZ series improved the basic principle of the compression algorithm. This paper details the various parts of the data structure and rtl implementation process, and based on specific principles and methods of each module, learn the VMM verification method based on the latest development of Synopsys, Inc., First analyzes the shortcomings of the conventional IC verification, then in simple terms the advantages of the System Verilog as a verification langusage, Specifically addressed the VMM verification methodology. Describes how to use the advanced verification languages, basic verification library and mature verification model, rapidly establishment of randomly generated test vectors, vector scene can be modulated, and collection coverage verification system. Finally with the design of Skcore subsystem, And in accordance with the need to implement the functionality of each module, Structures validation environment for verified Skcore subsystem use the high-level verification language system Verilog, Including the Implementation and debugging process of verification top-layer, Scene layer, command layer, functional layer, the signal layer and Test layer. Finally, for the target of coverage statistics, Analyzed to the verified results and coverage, And got a summary of the experience accumulated by the validation process and the verified results.