Intelligent And Efficient Processing Of Algorithm Track

Modern and advanced weapons systems development and high-tech warfare complexunder the conditions of the battlefield environment have an increasingly strong radar targetidentification Strong demand. Of the proposed intelligent and efficient processingalgorithms for the current track track encountered the reality of the problem Proposed, is aproven practical solutions. In the multi-target tracking system, the need for economical useof radar resources as the signal processing and the rapid development of computertechnology, target identification required real-time processing has become possible. On theone hand Target initial target identification, target characteristics to establish and update thedatabase for matching to achieve the target feature points-Air phase Off processing; onecan improve the rapid construction of aircraft, the other to ensure that goals are not lost inthe circumstances, improve tracking The number of targets, greatly reduce the false alarmrate, while also ensuring the track quality. This article first track from the point of startingtreatment, a detailed analysis of The target track features intelligent extraction methods,including point of trace detection, point trace gather (distance and azimuth), andsmart Feature extraction, and different characteristics of the target information analysis, andtarget classification, target characteristics to create a database. However, According to thefront of the trace point feature information for intelligent data handling track, a detailedanalysis of intelligent algorithms that track the real deal now.In recent years, with the digital signal processor (DSP) chip integration, computingspeed, data throughput and other performance continues to improve; DSP in high-speed,real-time signal processing has been more and more applications, which is smart track theimplementation process as possible. This paper describes a DSP+FPGA architecture basedon dual-track process of intelligent hardware platforms, including DSP chip chosen TI’sTMS320C6455, FPGA selected Altera’s EP2S90F1020. In the code composer studiosoftware development environment, through hardware design and software programmingintelligent track processing algorithms. Hardware design, including the connection betweenthe module and the module initialization method. Software design and programming,including the main program interrupt response and other routine design.