The Design And Implementation Of Blind Equalizer Based On Fpga

In the high-speed wireless digital communication, equalization techniques is usedcommonly to improve the unideal channel transmission characteristics. Blind equalizationtechniques can get the effective bandwidth utilization without the help of the trainingsequence. So it is widely researched. With the improvement of integration andfunctionality and reliability of Field Programmable Gates Array (FPGA), as well as thehigh operation speed caused by parallel computing hardware strncture, the application ofFPGA is increasingly broad in modern wireless digital communications system. Therefore,the main topic is the implementation of the blind equalizer based on FPGA in the paper.Firstly, based on the XC4VLX25 model FPGA of Xilinx Virtex-4 family, thisdissertation mainly discusses the design and realization of dual-mode blind equalizerwhich is a combination of Modified Constant Modulus Algorithm and Decision Directionalgorithm. With the top-down design methodology, the blind equalizer is divided into fourmodules: data delay module, filter module, error calculation module and the coefficientupdate module. Subsequently, the design methods in Verilog HDL of each module and thestructure diagrams of each module are given in detail. The function simulation of eachmodule is done with the Modelsim software to verify the dual_mode equalizer’sperformance.Secondly, some methods to improve the processing speed of the design system basedon FPGA are studied, due to the demanding for the data processing speed becomingincreasingly high in the communication system. Pipelining techniques and parallelstructure and algorithm optimization are applied in the design to improve the processingspeed of the design system.Thirdly, an FPGA implementation method of FIR filter in the adaptive equalizer isproposed, and applied to the FPGA implementation of the MCMA_DD blind equalizer.Moreover, simulation is done to verify the feasibility of the proposed design.At last, due to the constraints of existing hardware in the laboratory, the serialMCMA_DD blind equalizer and the serial MCMA blind equalizer are designed based on the XC2S300E model FPGA. And Synthesize, Place and Route, Static Timing analysisand simulation of the the design are done.At the same time, the analysis of timinginformation and simulation results and resource utilization is done to verify therealizability and the performance of the two design on the XC2S300E.