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Design And Realize Of Radar Intermediate Frequency Test Signal Source Based On FPGA

Posted on:2013-03-19Degree:MasterType:Thesis
Country:ChinaCandidate:Q ZhangFull Text:PDF
GTID:2248330362472180Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Signal source is an important part of modern radar system, during the radar testsystem, a signal source which could produce different test signal is needed. And radartest signal source which use direct digital frequency synthesize(DDS) as core, usefield programmable gate array(FPGA) as hardware base to be portable and low cost isthe direction of radar intermediate frequency test signal source.At first, the construction of DDS principle and DDS system was analyzed, theDDS system’s output spectrum in ideal condition and non-ideal condition wasresearched, finds DDS spectrum disorder’s main characteristic, analysis and comparethe effective storage capability which could increase waveform, joins jitter technologyand CORDCI algorithm of spurious suppression method. Secondly, using DDStechnology as core, a radar intermediate frequency test signal source system andhardware circuit of every module was designed, including FPGA module, D/A module,filter module and amplification attenuation module. The FPGA module includedpower circuit, clock circuit and download circuit. In the end, using CycloneⅡseriesFPGA chip EP2C8Q208C8N as platform, the design and realization of NIOS Ⅱsoft-core processor system, wave generation and wave modulation FPGA logicalfunction was finished. The wave generation is the key of FPGA logic design, mainlyincludes the design and realization of phase accumulator and sine lookup. The wavemodulation includes the design and realization of linear FM, nonlinear FM and phaseencoding.According to the test, the highest output frequency of the radar intermediatefrequency signal source reaches35MHz, frequency resolution is less than0.1Hz, frequency spectrum Signal-to-clutter ratio≥50Db,reach the design performance indexrequirement.
Keywords/Search Tags:DDS, FPGA, Verilog HDL, Spurious suppression
PDF Full Text Request
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