Research On Cascaded H-bride Of Seven-Level Inverter And Realization Of Carrier Phase-shifting

With the high power self-turn-off devices and intelligent high-speed microcontroller development, high power electronic converters are widely used. Since the multilevel inverter, capacity of voltage source converter is larger and larger; performance of voltage source converter is higher and higher. The research and development the control method of multilevel inverter, significance of technical and practical application are very important. DSP digital control technique is applied to the seven level inverter not only simplifies the hardware structure of the system and improve the performance of the system, but also realize the optimization of system control.In this paper, introduces three kinds of multilevel inverter topology and control strategy of PWM, through the simulation and analysis of the carrier phase shift and irregular sampling method to generate PWM pulse. The seven phase three-level inverter needs36PWM, but DSP2812is unable to meet the requirements, the DSP+FPGA structure is proposed to solve this problem, DSP as the main control chip, FPGA extends the PWM wave. DSP is responsibility for the calculation of sampling cycle and transmission the cycle value for FPGA. FPGA generates36PWM pulses by the data latch module, phase shift module and dead time module. This structure makes the circuit design is simplified and the reliability of system improved, meanwhile can ensure the triggering pulse to the switching element of the system synchronization.The hardware part includes, power supply module, signal adjustment module, IGBT module, DSP module, and FPGA module. Software is the use of C language and Verilog in CCS3.3and Quartus Ⅱ environment write.