Design Of Matrix Transpose Controller And The Implementation In Heterogeneous Multi-Processor System On A Chip

Synthetic Aperture Radar is one kind of advanced microwave observation equipment. It plays an important role in the national economy and military applications. The real-time imaging algorithm plays a important role in the synthetic aperture radar systems since it has real-time image processing capabilities. Nonlinear Chirp Scaling (NCS) is belong one of them. The real-time imaging algorithm typically include range compression, matrix transpose and azimuth compression. Matrix transpose is the connection between range compression and azimuth compression. The efficiency of Matrix Transpose has a great effect on the performance of the whole algorithm.NCS real-time imaging data processing algorithm mainly consists of complex operations, FFT/IFFT and matrix transpose. In order to meet the requirements of NCS imaging algorithm, this paper introduces a platform which is2D-mesh heterogeneous multi-core processors architecture. It contains two clusters used to calculate the cluster structure. The calculation cluster is used to calculate the complex arithmetic and FFT/IFFT, while the transpose cluster is focus on matrix transpose. This article introduces the cluster structure as well as for the various protocols of the platform. And parallelization divided NCS algorithm on this platform and achieve it finally. Matrix transpose is an important part of R-D algorithm.Due to the speed requirements of real-time imaging, Matrix transpose is generally implemented by hardware. The design methodology of a Matrix Transpose Unit is presented in this paper which is bus-based SoC architecture, using HW/SW codesign based on SRAM, after surveying a variety of matrix transpose method. It is Extensible and more flexible since it is controlled by embedded processor, compared to the other Matrix Transpose methods. It can correctly choose which method to use according to the size of Matrix. It can input and output the data packets at very high speed, since SRAM is chose as the memorizer and many peripheral units are used.This paper achieves the parallel data transmission for the matrix transpose controller based on the above presentation since the feature of SRAM. The controller adds a network interface and uses dual-port SRAM data transmission to get ping-pong data manipulation. And the transpose acceleration unit replaces the DMA greatly reducing the established link time. Thus transpose efficiency improved significantly from30%to80%. At present, this design is currently used in the NoC system, and has been worked well in the prototype demo system implemented with Xillinx V6550T FPGA chip.