Development Of Multi-drive System Based On Indirect Matrix Converter

The topology of multi-drive system based on indirect matrix converter adopts a structure of a rectifier stage connecting several inverter stages. Therefore it reduces the number of switches. And there is no bulky energy storage component in DC link, improving the power density of this system. In addition, the system has the advantage of high power factor and perfect input/output waveform. It is suitable for the occasion of cooperative control of multiple motors in AC motor drive system. The research subject in this paper is a multi-drive system which is consists of two inverter stages and this paper make deeply research of the modulation strategy, hardware design and software implementation of multi-drive system based on indirect matrix converter.Simulate the modulation strategy of multi-drive system using Matlab and the simulation results show the correctness of modulation strategy. The prototype of indirect matrix converter has existed. The structure of multi-drive system based on indirect matrix converter is designed and the structure diagram is given in this paper. And also, the paper introduces the topology of main circuit and selects the switches of rectifier stages and inverter stages reasonably. The signal flow chart is designed through the analysis and summary of system signal. Because of the special nature of the PWM pulse width distribution, the control circuit use DSP+FPGA structure and implement communication with three-bus method. In the DSP+FPGA architecture, the DSP calculate the duty cycle and sector number instantaneously and send results to the FPGA in the form of binary code via the data bus. And then, FPGA complete the four step commutation of rectifier stage and dead time commutation of inverter stage. Finally, output the required PWM signal.The paper analysis the program of DSP. In QuartusII environment, FPGA program is designed by VHDL language, and four step commutation of rectifier stage, dead time commutation of inverter stage and the top program of FPGA is simulated. The simulation results show the correctness and feasibility of the program of FPGA.