.cu / Low-k Dielectric Surface Contact Analysis, Chemical Mechanical Polishing

With the conductor width scale of Very Large Scale Integrated Circuit (VLSI)reducing to32nm or less, the speed of the chip will become slow because ofintegration improvement. In order to improve the speed of the chip, the onlyway is to reduce the capacitance between the wires. So Silica dielectric must bereplaced by low-k dielectric or ultra-low-k dielectric, and we should consider thesurface contact problem of low-k dielectric and Copper when the chip waspolished. The stress and strain analysis in wafer scale and line width scale modelwere done based on ANSYS finite element analysis software, and the influenceof the diffusion barrier layer to the performance of electro-migration in chip wasstudied in this paper.The Von Mises stress distribution on the contact surface under differentstress loads, the pad's Young's modulus and friction coefficient in wafer-scalewas analyzed. We got a conclusion that the higher pressure can increase thevalue of the stress, which means that the material removal rate was higher andalso it could make the surface uniformity better. The rigid polishing pad canmake the silicon wafer surface more smooth, meanwhile, The flexible polishingpad is conducive to the formation of the better even none defective surface.When the friction coefficient was over0.6, it had a greater impact on thepolishing results and resulting polishing rate lower.The Von Mises stress distribution on the surface in the times1.2s,3.6s,6swas analyzed in three different situations which the value of a was0.1,0.5,1.0(the line width of0.5μm,2μm and100μm) on line width-scale. We could seethat the stress maximum appeared in the depression boundary, and then rapidlyreduced, it indicated that the boundary has a maximum material removal rate.With the polishing time elapsing, the stress value would increase, a dish pitwould be seen between the two line width, thereby broken the reliability of thedevice.The experiment results showed that, the additional Ta diffusion barrier layerafter annealing at a certain temperature could effectively enhance the Cu interconnect's electro-migration performance, and the performance would alsoenhance with the increase of the annealing temperature at a certain rang.