Worst-case performance analysis of low-power instruction caches

This thesis aims at estimating the worst case execution time (WCET) of a program running on a processor with a decayed instruction cache. It extends the static cache simulation technique to set an upper bound on the execution time of a program in the presence of the cache decay technique. Experimental results on some sample benchmarks show that it is possible to accurately bound the WCET (close to 100% accuracy) for programs with single execution path. Moreover, for programs with multiple execution paths, it is also possible to reasonably bound the WCET but with less degree of accuracy as compared to programs with a single execution path.