High Efficiency Embedded Processor IP Core

In order to improve the performance of the embedded processor, we analyze the frequency and performance bottleneck of 32-bit embedded processor RISC32E, which is designed by the Media Processor Lab of Zhejiang University. We design a high performance embedded processor a deeper pipeline architecture, called Gemini. The Gemini memory system is then improved by a mechanism of hardware data prefetching. In addition, a RTL power model is designed to estimate the power of Gemini.The Gemini pipeline is partitioned according to the critical path of the memory access. Experiments show that with TSMC130nm technology, Gemini can work at 360MHz in the worst case, and 500MHz in typical case. Furthermore, the EEMBC certified ConsumerMark score for Gemeni is 0.11/MHz, which achieves 31.9% enhancement compared with RISC32E's 0.084/MHz. The EEMBC certified TeleMark score is 0.02/MHz, which achieves 66.6% enhancement compared with RISC32E's 0.0119/MHz.Gemini uses the hardware data prefetching technique to improve the memory performance. Based on Stream Buffer, the data prefetching mechanism uses the minimum delta stride to prefetch. By recording the address of the cache miss, the prefetching circuit calculates the prediction address, and prefetches the data to the cache. Experiment shows that Gemini with the hardware data prefetching mechanism achieves 2.1% performance improvement by Dhrystone test,3.3% performance by the EEMBC ConsumerMark,3.7% performance by the EEMBC Telemark.At last, this thesis studies the power models at different levels and the power-analysis methodologies, including the system-phase analysis methodology, the design-phase analysis methodology, the implementation-phase analysis, and so on. Furthermore, a power model based on RTL is built to estimate the power of Gemini.