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Research Of H.264 Decoder Based On ARM Embedded System

Posted on:2012-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:D LiFull Text:PDF
GTID:2218330362956449Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Because of high encoding quality, low bit rate and network-friendly, H.264 video encoding standard has been applied to CMMB (China Mobile Multimedia Broadcasting). As is known, the processor of cell phone has a low capacity of processing, while H.264 video decoding has high computing complexity, so the research about how to implement real-time decoding of H.264 has became a hot topic recently.H.264 video decoding is comprised of entropy decoding, reordering, inverse quantization and transformation, intra prediction, inter prediction, deblocking filter, management of reference frame, and so on. Through analyzing the H.264 decoding modules and character of ARM embedded system, two methods are proposed to optimize the H.264 video decoding, such as software optimization and hardware acceleration.There are three ways to improve the H.264 video decoding speed rate for the software optimization, which includes the algorithm improvement of interpolation and deblocking filter, assembler implementation of copy operation between macro block, the code optimization of reducing memory access and conditional branch. Furthermore, some methods of error resilience are put forward to improve the robustness of H.264 video decoding. The experimental results show that the optimized H.264 decoder achieve higher decoding frame rate for the video sequence of QVGA (320×240) format with no significant loss of image quality on ARM embedded system under frequency of 528MHz.The method of hardware acceleration takes use of hardware implementation of H.264 decoding module to decode slice data, while the module is listed as bit stream parsing, inverse quantization, anti-transformation, intra prediction, inter prediction and deblocking filter, in the meanwhile, software of H.264 decoding is responsible for decoding SPS (Sequence Parameter Set), PPS (Picture Parameter Set), slice header data and managing reference frame, moreover, hardware and software can communicate with each other via interface. Comparing with inter prediction and deblocking filter hardware acceleration, although the complexity and cost of the proposed H.264 decoding module are higher, the decoding speed rate can be much faster, and the H.264 video deocding module can be applied to decode CMMB bit stream.
Keywords/Search Tags:Optimization of H.264 Decoding, Embedded System, Hardware Acceleration, Error Resilience
PDF Full Text Request
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