Improved Algorithm And FPGA Implementation Of Particle Filter

Particle filter, a new filter method based on Monte Carlo and recursive Bayesian estimation, has special advantages in dealing with the state filtering and the parameter estimation in the non-linear and non-Gaussian system. Since the resampling algorithm was proposed in 1990s, PF algorithm obtained a rapid development. However, the drawbacks of complex algorithm architecture, enormous computation and low operation speed have restricted its implementation in real-time system. In order to reduce the complexity of the particle filter algorithm and improve the operation speed, this dissertation presents an improved particle filter algorithm which adjusts the step of resampling and weight calculating. And then a fast, credible and using few hardware resource's particle filter algorithm was designed to be applied to the real-time system, such as object tracking system.Field programmable gate array (FPGA) is a developed product of the programmable logic device PAL and GAL, which can implement the real parallel computation. In this dissertation, VerilogHDL is employed to compile and simulate on QuartusⅡdevelopment platform as a hardware description language. PF algorithm's hardware logic on FPGA is implemented in this way.First of all, the related contents and the basic theory of particle filter was introduced in detail. Taking the bearing-only system as the model, the basic flow of particle filter algorithm was given.Then, A new resampling algorithm which combined partial resampling with optimizing combination algorithm was proposed by improving weight calculating method. In terms of its weight, the particles were divided into three parts, and then particles which had high weights were copied and combined with low weights particle, while middle weights particles remain unchanged and low weights particles was abandoned. In this improved algorithm, the complexity of the algorithm was reduced without diversity of the particles lost.Finally, through analyzing the method of implementation in parallel, the functional module of the algorithm based on QuartusⅡdevelopment platform was designed. After that, the hardware structure with VerilogHDL was described and the validity of the algorithm was also verified.Simulation results and the report of the resource using condition show that the improved PF algorithm has characteristics of high operation speed and using small resource. It can be widely applied in real-time systems such as object tracking, image processing and parameter estimation etc.