The Fabrication And The Performance Study Of Ferroelectric FET With HfTaO High-κ Insulator

With the progress of communications technology, people have access to various electronic information services, unhindered by time and space. The core technology of electronic systems is that of semiconductor devices such as processors and memories. With the High-k/Metal Gate technology, the current technology generation has gone beyond 22/20 nm node. However, the continuing pursuit of performance improvements in CMOS devices through downsizing is approaching the limits, and various challenges at the physical and engineering levels have been identified. As an emerging non-volatile memory, FeRAM has the advantages of low power consumption and fast random-access, and has long been commercialized in fields such as portable electronic equipments and nonvolatile cache memory, suffering the problem of low density.The FeFET, on the other hand, with a much smaller cell size, is suffering the vital problem of short retention time. With an HfTaO film as insulator, the fabricated MFIS FET with Pt/SBT/HfTaO/Si gate structure has an excellent retention property. From the I_D-V_GS characteristics, it is observed that the memory window of the FeFET is 0.9 V and the drain-current on/off ratio is as high as 10⁷. Still, the I_D-V_GS curve remains almost the same after applying 2×10¹¹ pulses. If the FeFET is programmed with the pulse of 10 V and 1μs, the drain-currents of on and off state are 10^-5 A and 10^-11 A, respectively. The fabricated device exhibits excellent good drain-current on/off ratio of about 10⁵ after a 24 hours data retention test. During the endurance test, the memory window exhibits a slight reduction from 1.1 to 0.9 V after 2×10¹¹ cycles.Under the guide of proposition of FeFET NAND Flash ROM, the feasibility of FeFET NOR Flash ROM is discussed. After that, a novel layout-wiring for the memory cell is proposed, namely dual-bitline structure. With the new layout-wiring, the FeDRAM is capable of synchronously random accessing, and also could be equipped with a refresh scheme. The flexible programming lays a good foundation for the refresh of the FeFET cell in an FeDRAM. The physical-level short retention problem is eventually overcome by a circuit-level solution.