Research Of The Mechanism Of Tolerance Based On FPGA Fault Detection And Localization

As the Field Programmable Gate Array has the characteristic of multi-programmable,flexible structure and high reliability, which are used in large digital systems. Therefore, once the digital system fails, it will cause the great losses in people and property, that high reliability. In the real application, conventional fault-tolerant methods cannot satisfy the actual requirements, so we need a new fault-tolerant method to improve the results. Therefore, this thesis have some research of FPGA chip with limited resources, overcome the defects of high-quality chips about system errors under a long time or the increase defects in system size, weight and cost by enlarge system backup and redundancy based on exploring a new FPGA fault detection method, and explore a new method based on the FPGA fault detection.Through, analysis the background of high reliability system application, with FPGA chip architecture, this thesis presents a diagnosis method to enlarge defecting t coverage and settle the accurate location. According to multi-programming of FPGA, the method increased the types of programming to further improve fault coverage and accuracy of fault location.Based on analysising typical FPGA fault detection methods, this paper explored the design of configuration data-based fault detection method, design three functional modules and complete the simulation.In summary, it explore key issues of configuration data-based fault detection method.