Communications Network Of Reliable Data Transmission Control Strategy And Implementation

The rapid developments of internet technology with each passing day have led to exponential growth of the requirement to high-speed communication network. But the scale,task and capacity of communication network have grown increasingly,the kinds of machines together also differ in thousand ways,and some special communication systems have worked in stable environment,which makes the probability of making a mistake to physical link layer or computer system more and more bigger. So the research to the reliability of high-speed communication network has become a hotspot of the research on internet technology.The thesis thoroughly study and design the message transfer and error correction protocol of link layer of interconnection network. To ensure the high-speed and no error transfer of data in link layer, we start with the reliability of error control and flow control, bring forward the blue print of the 64 bit parallel cyclic redundancy checkout and the retransfer queue based on sliding window protocol, and then finish the design,simulation and implementation of FPGA.We first discuss the principle of error control and many kinds of error detection or error correction technology such as odd-even checkout, haming checkout, CRC code, RS code and so on. Secondly, we compare the performance of different checkout code and point out why the system adopts the CRC code and retransfer for the error control.Many systems adopt the serial CRC, which has high requirement of frenquency .The paper study the principle of parallel CRC, and then study the implementation of the 64 bit parallel CRC circuit by an example, and validate the feasibility of fact circuit by simulation, synthesis and implementation.For the retransfer and flow control, we first study its principle and some important types such as strategy of XON/XOFF, sliding window protocol and so on ,and then sort out the blue print of sliding window protocol which accords with the requirement of the interconnection network system for the decrease of transfer delay. We lastly discuss the key technology and FPGA design scheme of retransfer queue based on sliding window protocol, and validate the feasibility and correctness of logic design by simulation and synthesis.