Deep Sub-micron Integrated Circuit Interconnect Resistance Exception Analysis And Their Solutions

With the era of integrated circuit's technology node entering into deep sub-micron and below, line width is continuously decreasing. RC delay from the Contacts and interconnects have become the most important factor influencing the integrated circuits' performance. Self-aligned CoSi2 on the source-drain regions plays the role of decreasing contact resistance. As material connecting metal lines, tungsten has excellent step coverage and superior electromigration property. In wafer manufacturing process, the abnormal resistance of these two materials will directly affect products' wafer acceptance tests, leading to low yield. Removing the phenomena of abnormal interconnects resistance will be a great help for enhancing products reliability and yield.Interconnects act as the passage to connect devices. With the diminishing of devices' sizes, interconnects need to decrease contact resistance so as to reduce signal delay. Looking for materials of lower interconnects resistivity and lower dielectric constant has been a research area for deep sub-micro and nanometer devices. In 0.18 and 0.13 microns CMOS fabrication, PVD cobalt and salicide technology are used to form the interlayer between device and contact. CVD tungsten is also used to be W plugs between the silicide and the metal 1 to form interconnects between devices.The phenomenon of abnormal resistance is often observed in the process of metal silicide and interconnects, resulting in signal delay as well as affecting devices' yield and reliability. This thesis introduces wafer fabrication process and investigates abnormal resistance of silicide and W plug process on production line, including: (1)the relatively high sheet resistance of CoSi2 when Co target getting close to its life time; (2)abnormal sheet resistance of CoSi2 in single wafer; (3)high contact resistance of CVD tungsten film in first wafer after clean; (4)abnormal contact resistance induced by W void. With analyzing experiment data, the thesis also provides some ways to solve these problems:(1)periodically tune spacing of machine and change measure points of Co film thickness when Co target getting close to its life time; (2)modify process recipe of Co deposition and system configure setting of its machine; (3)optimize clean recipe of CVD tungsten; (4)optimize CVD TiN process recipe and process flow of CVD tungsten. Thus, the products' yield is enhanced.