Design And Implementation Of A Remote Soc Simulation Accelerator

Comparing with traditional Application Specific Integrated Circuit (ASIC) which comprises a mass of hardware modules, System on Chip (SoC) integrates software such as operating system, driver, protocols and application programs. Thus, SoC is much complex for design and difficult for verification. The functional verification has gradually become one of the bottlenecks for SoC design, due to the increasing complexity in both hardware and software, and the increasing interaction burden between them. In order to exploit SoC efficiently, various simulation methods have been proposed, among which Hardware/Software (HW/SW) Co-simulation has a bright prospect.In this paper, a SoC verification accelerator based on networks is proposed, which is designed based on the theory of co-simulation of HW/SW. It utilizes a debugger to interconnect the server and the design under test (DUT) on remote FPGA board. The debugger, which is composed by ARM and FPGA, establishes a real-time bidirectional data path and completes the data conversion. The embedded interface module can be synthesized with user's DUT smoothly. In our platform, the software design can be simulated in the server, while the hardware design can be simulated in FPGA board which gives a more reliable result. And the hardware environment can be shared among geographical distributed users through remote interaction with Internet. And this platform is flexible to use and easy to extend. The main works can be summarized as following.1. Introduction of the method related to SoC simulation and verification acceleration technology.2. The overall design idea and features of the accelerator.3. The key points of the software system design and the details of the communication protocol and data format between software and hardware systems.4. The design and implementation of the hardware system.5. Co-debug of the software and hardware systems, verification of the accelerator's function and test its performace, analysis of the simulation speeds and our plan for improvements.