Embedded Operating System For Multi-core Processors

The main purpose of this thesis is to study what changes should be committed onμCLinux to runμCLinux on dual-core Blackfin 561 DSP. The concentration of this thesis is focused on following areas, booting, interrupting, and cache.The main work of this thesis on booting is, constructing a kernel thread after core A initialized, which will copy initializing code for core B to appropriate memory location. The kernel thread will proceed to install service routine for inter-processor interrupt, and then finally kick off core B. The initializing code for core B derives from initializing code for core A. Initializing work comprises of, installation of interrupt service routine, enabling cache for core B, reserving private data area of core B, and setting timer.Two affected interrupts in this thesis are inter-processor interrupt and timer interrupt. Data structure and corresponding functions needed by inter-processor interrupt are constructed and established in this thesis. As for timer interrupt, core A and core B share the same interrupt service routine, no special treat is needed, so we just give it a short glimpse.To enable cache on core B, two tasks are undertaken in this thesis. CPLB data structure which is suitable both for the dual cores is added. Moreover, loading and switching CPLB is implemented. CPLB data structure is involved mainly in representing and storing CPLB. On the other hand, loading CPLB means writing to CPLB table in MMR and switching CPLB means switching in and out CPLB to MMR in a given policy. Cache coherence and atomic operation under cache situation is added as supplementary.Finally, this thesis ends up with testing of the modifiedμCLinux. The adopted testing program is based on BBP algorithm for pi. We stated and proved BBP formula. Detailed scheme for parallel BBP algorithm is explained. Conclusion about the testing result is made at the end of this thesis.