The Universal High-speed Telemetry Receiver Bit Synchronization Board Design

The telemetry receiving system is one of the key backup systems in receiving the remote dynamic target information. The bit sync signal from the bit synchronizer takes the key function of demodulation treatment synchronism reference and it is the base for the subsequent picture format demodulation and data processing. Though the bit synchronism technology in the general communication system is comparatively completed, the various bit synchronism technology which is based on the PCM used in the aviation and astronavigation telemetry system still needs further research and development. So far, there is no commercialized bit synchronizer, while the bit synchronizer from the foreign country has been equipped with various functions, the price is too expensive. As above mentioned, it is a must that China should develop its own bit synchronism sheet.Firstly, this essay introduces the background of bit synchronism sheet by talking about the developing condition of the wireless telemetry receiving system and what the position the bit synchronizer has taken in that system. Then, the author talks about the concept, the basic method of bit synchronizer. Third, it introduces the design and realization of the bit synchronizer circuit based on phase lock loop method, putting great emphasis on the logic design and timing simulation. The bit synchronizer proposed by this paper consists of integral filter, symbol period estimation circuit and digital phase lock loop circuit. The integral filter is composed of integrator and hysteresis comparator, which can filter the short pulse near data edge. The symbol period estimation circuit measures the symbol period by moving average operation, which makes the symbol period measurement more stable. In the digital phase lock loop circuit, this paper put forward the statistic circuit to statistic advanced or lagged time which can prolong the hold time of the bit synchronizer.The traditional sheet adopts the PCI interface as the communication interface to the computer. While under the circumstance of miniaturizing and mobilizing of telemetry receiving system, the author chooses the USB2.0 as the communication interface between the bit synchronizer sheet and the computer. This essay introduces USB2.0 bus after the introduction of the design of bit sychronizator. Then, it introduces the controller CY7C68013 core which is used to integrate the USB2.0 interface. At last, it introduces the firmware programming of CY7C68013 core, the driven programme design of the WDM equipment on the computer end of USB2.0 interface and the application programme design at the computer end.At last, it introduces the hardware design and test. The bit synchronizer method mentioned in this essay is well proven on the Cyclone II Series EP2C5Q208C8 Type FPGA of Altera. By hardware testing, the synchronizing data code rate of the bit synchronizer circuit is from 5Mbps to 15Mbps. Actually, the USB2.0 on bit synchronizing sheet can transfer the recovered data from bit synchronizer circuit. The driven programme of USB2.0 at the computer end can identify the bit synchronizing sheet; the application programme can operate the synchronizing sheet and can realize the transfer of the high speed data. The simulation and actual test can prove that the design has achieved the target.