High Efficiency Of The Phase Modulator

This thesis describes the results of a study of the main specifications and the CMOS chip design of a high efficiency phase modulator for use in a LINC transmitter. First a system level simulation model representing the main building blocks of the transmitter chain is derived. This model consists of the power amplifier (PA) line up and the modulator and is used to investigate the relation between the modulator characteristics and the performance of the overall system. These relationships are subsequently used to derive the target specification for a number of critical modulator parameters from the 3GPP system standard. Next, a novel concept for modulation and power control of the PA line up is derived and evaluated by simulation of the most critical parameters. The requirements on the input baseband signal bandwidth are also estimated.This study indicates that the selected topology is capable to function as a high-efficiency LINC transmitter. The system is able to handle certain phase mismatch errors caused by the difference in electrical length between two PA branches. Amplitude mismatch errors at high power levels are constrained by the inherent property of the saturated PA.For circuit design, detailed efficiency analysis, performance comparison and simulations resulted in the selection of a novel Class-B input switched transconductor mixer based phase modulator concept. The simulation results indicate that the high efficiency LINC modulator is capable to provide high output power with relatively high efficiency. Other parameters like in- and out-of-band noise also meet the system specification. Simulation results of the other needed functional circuit blocks like the voltage-to-current converter and frequency divider are also given.Two test chips for evaluation of the high efficiency LINC modulator have already been fabricated. Recommendations for future work are given in the end.