Array Speech Enhancement Algorithm And Realization

Speech enhancement is to get original speech as purly as possible from the noisy sound, to upgrade the speech quality, and to improve the clarity for recognition and acceptence. Speech enhancement with microphone arrays, an important branch of array signal processing, is the method of achieving spacial smapling with separated multiple microphoene elements as sound collectors, inhibiting the interference and background noise from non-speech direction by the spacial difference between objective speech and interfence/noise, and improving the SNR (or SIR) of the output signal by beamformings and other array signal processing means.In this thesis, we focus on the algorithms of speech enhancement using microphone array, especially the generialized sidelobe canceller (GSC) and its subband flittering algorithms, based on which we proposed an improved subband adaptive generalized sidelobe cancelling algorithm, that is to calculate the error signals respectively in each subband, and update the coefficients of adaptive filters using the information of whole band. With the experimental data of Carnegie Mellon University's microphone array speech database and signals obtained by a self-developed SOPC-based digital speech collection system, the performances of the improved algorithm is compared with those original ones. The results indicate that the improved subband adaptive GSC algorithm has a better segmental SNR and Iitakura-Saito distance, especially in a low SNR environment and conditions with color noise.Besides, based on DEII development board provided by ALTERA Company, we studied the speech collection and enhancement system implementation with SOPC technology. To achieve real time processing according to application requirement, we tried to find a balance between the softwere and hardware constraints. We properly used both NiosII embedded firm core and the remaining FPGA resources, while utilizing multichannel high-efficient FIR system structure with multi-phases in sampling rate convertion and multiplexing technology. The design is real-time implemented at a 100MHz system clock with effective and efficient use of chip area. It's expected to be the foundation study for further applications.