| Dynamic Random Access Memory(DRAM) is the most important memory device in PC application,which is used for read and write,The design of DRAM is moving to the high density and high memory size under the rapid competition,to gain more marketing share and profit,and the DRAM technology will go to a new generation in almost every 3 years.The high density memory size and CD scaling down also bring great challenge on the manufacture of semiconductor,all of the DRAM suppliers have to pay much more investment on the equipment and technology research to pick up this fast DRAM developing trends.The process of DRAM manufacture can be divided into below modules: Capacitor,CMOS Transistor,Interlayer Isolation,and Metallization Inter Connection. In those key process,increasing of capacitor,improve the transistor performance and control to lower leakage of interlayer and metal line,process induced capacitor,all of those issue became the hot topic to support the scaling down of the technology and achieve the higher and stable yield.This paper is based on Deep Trench DRAM manufacture technology,studied the BPSG void issue in the 0.11um DRAM mass production process.With the help of DOE and many process tuning,we find the optimized process condition to maintain the BPSG process to get void free and stable performance.Base on the study,we find BPSG void is mainly driven by the deposition condition and reflow condition,it is also very sensitive to the wafer pattern profile before BPSG deposition.Not perfect BPSG with tiny void issue can be enlarged after some WET clean and ETCH process so that will impact on the chip function and wafer yield.In our research,several BPSG deposition process parameters were studied;the deposition temperature and deposition rate can help to get good gap fill performance of BPSG.In the mass production,better control the chamber heater performance and lifetime will get better BPSG gap fill performance and stable yield.Increase B% concentration can also help to gain lower reflow temperature and better gap fill ability. But there is still some bottle neck when the Aspect Ratio come to a certain level which is hard to covered only through BPSG deposition step tuning,a reflow process improved function was found in our research.In normal reflow for BPSG process,use N2 anneal or steam anneal,steam anneal has better performance than N2 anneal.In 0.11um DRAM process we studied,even steam anneal can not fix the void issue, there is still some failure ratio,new finding is the introduction of 2 steps of anneal, dry anneal and steam annealing,it shows perfect void free and seam free BPSG film. After a huge volume of data collection,the BPSG void issue caused product yield loss was improved from 6～8%failure ratio to 0%.Each of the solution of above will impact the CMOS transistor out put,more or less.Like the threshold voltage,junction resistance,contact resistance.We need add some tuning base on the product characters to keep the original CMOS performance.There is also another method can help on the BPSG GAP fill issue.With first thinner layer deposition with lower deposition rate and then etch back a little bit to open the void inside of the film,the do a 2nd deposition step.It can also get help for void issue but make the process complex a bit. |
