Ultra-narrow-band Phase-locked Loop In The Digital Speed Ranging Receiver

Range and velocity measurement plays an important role in deep-space measurement. Traditional deep-space measurement systems based on analog technique have many limitations in expansibility,maneuverability and performance.With the rapid development of digital device and signal processing technology,the analog deep-space measurement systems are replacing by digital ones.The digital very narrow-bandwidth Phase-Locked Loop(PLL) is designed and realized for the digital range and velocity measurement receiver.The very narrow-bandwidth PLL is adopted as effective means to improve detectability of weak signal and precision of measure in deep-space measurement.The bandwidth of traditional analog PLL is limited and its reliability and stability are not good.The digital PLL doesn't have the limitations above.In this thesis,the PLL for range and velocity measuring is studied and realized which is used in the digital intermediate frequency range and velocity measurement receiver. Meanwhile,some conclusions and achievements are gotten.The main content of the thesis is as follows:(1) This thesis investigates the fundamental theory of PLL,in which we place stress on the PLL structure which is suitable for software implementation.By comparing linear and digitized PLL's phase-transfer function,a scheme of digitized PLL's design is given,the computer simulation is implemented.(2) According to the project's requirement,the technological difficult points are analyzed while realizing it.A realization structure of the digital very narrow-bandwidth PLL is proposed for the range and velocity measurement receiver,the main characteristic of the structure is that it uses the idea of frequency-leading and secondary-mixing,and systematic block diagram is provided.(3) According to requirement of design,the function modules of the digital very narrow-bandwidth PLL are analyzed and realized with FPGA.The system testing of the PLL is carried on,and the experimental results are analyzed.The result of experiment indicates the CNR threshold of input signal is 30 dBHz,and the minimal bandwidth of main side-tone PLL is 1.3Hz.(4) The general work of this thesis is summarized and the further research direction is pointed out.