Fpga-based Image Compression Card Design

Nowdays, the CCD camera in our country can export video signal and digital image signal. The video signal can display on the screen directly, but the digital one can not be transported easely because of costing too much memory. In this paper, a novel vedio compression card which based on the FPGA will be designed.In the past about ten years, a series of international video coding standards are developed and widely used in a variety of domains. H.264/AVC is the newest standard approved by the ITU-T and ISO/IEC organizations, which represents a number of advances in video coding technology and becomes the newest international video coding standard because of both high coding efficiency and network friendliness The design of H.264/AVC is based on conventional block-based motion-compensated hybrid video coding concepts, but with some important differences relative to prior standards: enhanced motion-prediction capability; a small block-size exact-match transform; adaptive in-loop deblocking filter; enhanced entropy coding methods. The experiment results show that the improved coding efficiency, up to 50%, comes with a complexity increase of more than one order of magnitude at the encoder. In fact, a proper use of the H.264/AVC tools leads to roughly the same performances as the complex configuration. So both computational complexity and coding efficiency should be thought and made to the optimal trade-off in the implementation of actual coding system.The emerging H.264/AVC has achieved significant improvement over the existing standards in the compression performance. But its high complexity prevents it from being used widely up till now. In this paper, the complexity of H.264/AVC is briefly analyzed, and some optimization approaches are proposed.The new features of H.264/AVC increase not only the complexity of coding basic modules, but also the one of algorithms by times. The multimedia instruction may be used to optimize the basic modules; the fast algorithms are developed instead of the old ones. This dissertation is based on the above methods, and major works are as follows.To reduce the complexity of deblocking, a hardware-fixed algorithm is proposed; it not only effectively in hardware cost but also achieved the capability of spec. To reduce the complexity of transform and quantization, a novel architecture has been proposed, it can match the pipeline of the architecture rightly, so the cost of hardware can be decreased efficiently. Simulation results demonstrate that these proposed methods can realize the H.264 real-time encoding of 720pHD format sequence. We also researched the encoder of H.264 (baseline profile), and proposed a hardware architecture, which can achieve as much as or better encoding performance compared with other encoders.