Key In Of B3g Tdd

In the movement, wireless communication has been developed rapidly and the GSM/CDMA mobile system can not satisfy all requirements. Recently, the need of high-speed data transmission and multimedia services make Multiple-Input Multiple-Output (MIMO) technique and Orthogonal Frequency Division Multiplexing (OFDM) become hotspot in the field of wireless communication. MIMO-OFDM has been regarded as the key technology of B3G communication system because it can improve system capacity and spectrum efficiency. Consequently, channel estimation, as a key technology of MIMO-OFDM system, has very vastitude foregrounded and been attended diffusely. Then channel estimation is significant to B3G system.During the National"863"FuTURE Project, UESTC is in charge of the B3G TDD downlink that bases on FPGA. The downlink consists of five boards which are responsible for digital-baseband transmitting, multi-antenna transmitting, multi-antenna receiving, channel estimation and MIMO, and digital-baseband receiving respectively.This paper is responsible for channel estimation and MIMO board and has finished the FPGA design of channel estimation. Simulation and testing results have proved the performance of B3G downlink.Chapter one reviews the development history and research actuality of wireless communication. At the same time, the characteristic and key technologies of B3G have been introduced. At last, the background of this dissertation has been presented.Chapter two introduces the characteristic of wireless channel. Specially, the fading distribution of small-scale has been presented.Chapter three describes the common algorithm of channel estimation in OFDM system. Consequently, the algorithm of channel estimation based on Pilot Symbol Assisted Modulation (PSAM) in MIMO-OFDM system has been introduced detailedly. At last, a two-dimension algorithm is employed in B3G downlink for channel estimation.Chapter four is about the FPGA design and realization of channel estimation of B3G downlink. After introduction of the whole FPGA design of B3G downlink, chapter four schemed out every function module such as frame disassembly, frequency domain estimation, time domain estimation, and phase equalization etc. Lots of structure schemes were presented and the resource report of synthesis has been presented.Finally, in chapter five, we summarized and concluded the whole dissertation. Further research issues and possible research directions were pointed out.