Ipv6 Packet Processing Protocol Stack Implemented In Hardware Technology

With the development and the application of Internet, the Ipv4 addresses are increaseingly facing the problem of depletion. So IPv6 is proposed by IETF as a major next generation network protocol. IPv6 address space is extended to 128 bits, both security and automatic configuration of mobile node have been well supported. As for the optimization of the dataflow process-oriented network, network processor will be more and more frequently used in the network core equipments. In order to deploy IPv6 network, it is a necessarity to achieve network processor agreement on IPv6. Especially in the backbone network node, it is important to study and realize a high-performance IPv6 data packet hardware protocol stack modules, which is a reliable technique support for Ipv6 commercialization and intellectual property in China.This paper presents the "The Research of hardware Technology for IPv6 data packet process stack" issue, addressed from the Northwest Polytechnical University aviation Microelectronics Center research project on "Research and Application of High Performance Network Processor ". Aimed at dealing with IPv6 network protocol processing and optimized performance of protocol process for Network Processor, it will serve as a coprocessor integrated in the network processor.In this paper, a hardware protocol stack implementation is described, including the link layer protocol, IPv6, ICMPv6 module and the expansion of the UDP. Like other protocol stack, the design of this hardware protocol stack was leveled and modularlized; Employed with top-down design method and hardware description language, the modeling of this hardware protocol stack was built. Then the finished benchmark testing procedures are functional simulated and verified. At last the hardware stack was synthetized by EDA tool. The final results showed that functional verification is accorded with the expected design. It can achieve the highest frequency of75.861MHz.