Optimize The Design, Based On The Pci Interface Of The Digital If Receiver

With the fast development of Software Radio technology, the digital receiver systems are coming to play a major role whether in the communication systems or in the radar systems. It is expected to be designed based on the Software Radio technology in order to define the function of the hardware by the software, which can greatly improve the facility and the reliability of the systems. This subject has completed the research and development of a digital IF receiver based on PCI bus, associating with the project requirements.This subject has analyzed several models of the digital receiver, and compared their characteristics. It chose the poly-phase filter structure as the theoretical basis, and put forward an optimum design of mathematic model. It adopted the structure of decimate-filter-mix, and duplicated the filter bank, so reduced system resource efficiently, and improved the performance.The next step was to select the suitable hardware platform, and to realize the needed digital receiver. This subject has adopted the Top-down design flow to perform system designing and budgeting, setting the system clock and its running mode. The function, timing and interface mode of each module were also set. Verilog HDL was used to design and simulate each module in ISE and ModelSim, referring to the standard FPGA/CPLD design flow. ISE was used to connect each module, and complete the FPGA program design, implementation, simulation and timing analyze of the whole system. Finally design file was converted to a downloadable format.In order to meet the signal processing,data transfer requirement, and also make the system general, PCI bus interface have been designed, the device driver program and user application program have been developed. Finally the system test has been performed , the system performance through the results have been analyzed.This subject used ISE from Xilinx and ModelSim from Mentor Graphics to perform the design and simulation of FPGA programs; selected the Spartan-3 series FPGA (XC3S400) from Xilinx as the target device in the digital receiver, and selected the PCI9054 from PLX to implement PCI bus. It achieved the design objectives finally.