Study Of High-precision Cmos Reference For The Adc System

The increasing digitalization technology of telecommunications systems and consumer electronic appliances requires higher performance analog-to-digital converter (ADC). Reference is the key part of ADC, not only providing the bias voltage and current for the system but also playing the part of the compared voltage and subtracted voltage. Its performances are so important to the ADC system that the research of the reference becomes crucial.Firstly, based on the principle of the band-gap voltage, a high performance voltage reference is produced in this paper, considering the influence of the operational amplifier's offset voltage and 1/f noise. Based on the SMIC CMOS 0.35μm model, simulation results in Cadence Hspice indicate that the current reference has a temperature coefficient(TC) of 6.9ppm/℃over the temperature range of -40 to 85℃and a power line regulation (PLR)of 10.6ppm/V for a supply voltage of 3.0 to 3.6V.Secondly, A new CMOS current reference solution is presented, by creating a negative temperature coefficient current resulted from positive temperature coefficient resistor and the produced voltage reference, and proposing low line regulation mechanism which is realized by compensating variations of source-to-gate voltage and threshold voltage versus supply voltages. Simulation results show that the current reference has a TC of 6.9ppm/℃and PLR of 10.6ppm/V.Thirdly, a model of reference voltage buffer is set, in which the buffer with the impendence load of resistor and switch capacitor is analyzed in detail and the relationship between the speed and resolution of ADC and buffer's gain-bandwidth and transconductance is obtained.Fourthly, based on dividing the bandgap voltage reference with resistances and eliminating the current mirror mismatch, a novel differential reference voltage generator is presented. Additionally, a big capacitor and a impendence changing resistor is added to eliminate the influence of switch capacitor and high frequency noise. Simulation results indicate that the differential reference voltage has TC of 4.6ppm/℃and PLR of 1581.5ppm/V. Lastly, according to the mixed-signal system layout strategy, the layout of these circuits is designed and checked, with SMIC 0.35μm 2P4M mixed-signal CMOS process.