Narrowband Ldpc Decoder - Error Test Experimental Platform Design

This master's degree thesis firstly introduces and discusses the principle of OFDM and the merged blue print for digital terrestrial television broadcasting in china,then proposes a scheme for the test platform of narrowband LDPC decoding efficiency based on FPGA. This scheme includes techniques such as time-domain synchronization using PN and power estimation using pilots.According to the function of test platform, the test platform is partition into a few modules. Those modules are designed with verilog HDL and the key problems are discussed in details. The verilog codes for transmit and receive end of test platform are simulated under Quartus II 5.0 ISE, and debugged by downloading the verilog programs into EP1S25F780C and EP1S80B956C6 developing kits. The result shows the system works.This test platform is simplified OFDM digital television transmission system. The test platform provides a quick and efficient tool to testing the efficiency of LDPC coding for the setting up of DTV standard, without the need of the completing whold DTV system, saving time, improving work efficiency. Even this platform is simplified version, but it still has all the key technique of DTV transmission system, accumulating experiences for the design of DTV transmission system, and it can easily expands. The research in this thesis has great market value.