Simulation And Verification Of Floating-point Addition And Subtraction

High-Precision Computing, Graphic Acceleration, Digital Signal Processing and other applications require further improvements of floating-point processing. Therefore, Floating Point Unit has become one of the most important components in current microprocessors. However, as the design of FPU has caught tremendours attention, the verification of FPU lacks corresponding attention.This thesis is part of the National Defense Preliminary Research Project (Project number. 41308010108) in the 10th Five Year National Plan undertaken by the Aviation Microelectronics Center in Northwestern Polytechnical University. The LongTium R2 microprocessor is completely compatible with PowerPC 750 in interface and instruction sets. This paper mainly discuses the simulation verification of the floating point addition/subtraction.This paper,Sets up a verification environment in traditional Golden Model Method,Divides the model into 0*model, 1*model, and 2*model, and generates testvectors respectively,Solves the Mask Constraint problem: designs two separate fixed point number generator, and divides addition/subtraction into different categories according to their own characters, therefore utmost utlizes their individuality, which leads to significant computation cost,Solves the Range Constraint problem to construct testing vectors;With standard CMOS cell library in SMIC 0.18um, the synthesis results show that the FPU key path is less than 4.29ns, which satisfies the requirements of the main frequency of 233MHz of LongTium R2. The research work discussed in this paper provides important reference and experiences for designing and verifying future high-perforamcne embedded microprocessors with own Intellectual Property Rights.