Speed ​​(6mbit, / S), Research And Realization Of The Bit Synchronizer

What this paper accomplished is the research and accomplish of the high-speedbit timing recovery in the digital communication.The timing recovery is one of the crucialtechnologies and difficult poits in digital communication .After thoroughly study the relatedknowledge of the timing recovery, I analysis the commen timing recovery in the communicationnow, then upon this basis, analysising the phase-locked method of the self-synchronizationrecovery, introducing the fundermental of three kind of phase-locked methods, then comparingthe performance and applicable scope; In the end I choice one of the three schemes and it hasgood performance, that is the timing recovery based on interpalation, the arithmetic design inmatlab as well as the simulation and the analysis are discussed, the verilog realization of timingrecovery is completed.Secondly I introdce the filter method of the self-synchronization, that isone bite PN code timing recovery, it's fudermental as well as softe simulation ,hardwareimmplemention and it's performance are discussed. Finally, the circuit board is designed, thesoftware and hardware debugging is performed.What I have done in this subject include:Analyzing two kinds of methods of the timing recovery in fundamentals performance and applying scope.Complete the arithmetic design of the timing recovery .Carry out the soft simulation and analyze the resu1lt.Carry out the software design of the timing recovery based on interpalation and the 1 bit PN code timing recovery.Using PROTEL to generate schematic and PCB layout, debugging the software and hardware and accomplishing the debug on the whole system.