Based On The Soc Of Hdb3 Encoding And Decoding And Frame Synchronization Circuit

The subject described here is a redesign work for the project of The Communication Theory Experiment Equipment. The equipment is used to study the theory of communication for the student learning major of communication engineering or correlative professions. The original design is realized by traditional way which is based on discrete chip combination and usually called "Bottom-Up" design. The aim of this project is to redesign all experimental circuits by the way "Top-Down". Since the "Top-Down" way starts from the function of a circuit, all designs could be combined in one PLD chip and realized an SOC (System on a Chip). This paper focuses on HDB3 decoder and the frame synchronization circuit redesigning.The traditional way of "Bottom-Up" design requires that the designers are familiar with the bottom chips, and it's disadvantages are usually complex designing process, large workload and the little possibility of migrating. Moreover, along with the high speed development of SOC design technology, the ability of SOC design based on FPGA is increased greatly. The design based on IP core will improve the exploitation efficiency, it is becoming one sort of mainstream method. At the same time one of the remarkable characteristics of modularized chip is easier to increase new function and shorten the time to market. Depending on the technology changes, there is the possibility of upgrading the original design in order to match the changes. The task is divided into circuit blocks according their function. After realization of functional circuit blocks, all experiments of the equipment will be integrated in a single chip. Hopefully, the new designs will be acted as a base of IP core.Two goals are proposed in this paper. The first one is to realize function of HDB3 decoder. Based on the principle and its VHDL description of HDB3, the circuit logic function is given. The design process including compiling, synthesizing and simulation supported by EDA tools, and the result shows that the design matches the function requirements.The second goal is the realization of Frame Synchronization circuit by EDAtools. The design uses the multilayer function of the software MAXPLUS II, and divided the circuit into five parts including Identification , Frequency division, Frontage protects Backside protect and Trigger. The first step for this design is to describe the separate parts by using VHDL. After the process including compiling, synthesizing and simulation supported by EDA tools, all the parts are combined with graphics and composed the top circuit. At last, the system simulation is carried out. The result shows that the design matches the function properly. The process of the design shows the validity of the "Top- Down" way.