Design And Implementation Of The Usb Interface Circuit - The Receiving End Design

Universal Serial Bus(USB) is new technology about interface in computer application．USB has been used widely since the windows operation system supported the USB interface in computer． The major goal of USB was to define an external expansion bus which makes adding peripherals to a PC as easy as hooking up a telephone to a wall－Jack． The program's driving goals were ease-of-use and low cost． These were enabled with an external expansion architecture．Universal Serial Bus(USB) is one of the most important developments in PC peripheral Interconnect technology since the introduction of serial and parallel ports in the early 1980's．The benefits of USB,such as ease of use, plug and play,high performance,and reduced overall system cost,are just a few of the reasons this technology has gone from specification to product development in less than 2 years. it supports low speed (1.5Mb/s), full speed(12Mb/s)and high speed(480Mb/s)data transmission. The USB devices can be connected with the PC on the computer's USB interface, and also connected with PC through the HUB. So the USB is widely used.This paper mainly introduces the USB work principle ,the communication protocol of USB,bus system structure, data transmission method, data flow model of USB. An idea is brought forth to design the total structure of the USB interface IP, the main control logic , the MCU interface (the function is the same as the PDIUSBD12 chip of the PHILIPS semiconductor) and a DPLL which is used to synchronize data and separate the clock. This paper also introduces Packet recognition, transaction sequencing, SOP, EOP, RESET, RESUME signal detection/generation, NRZI Data encoding/decoding and bit-stuffing, CRC generation and checking (Token and Data), Packet ID (PID) generation and checking/decoding,Serial-Parallel/ Parallel-Serial Conversion. The function controller of USB (receiver part) is developed in Verilog which is a widely used hardware description language, and simulated in Active-hdl and synthesized in Synplify, based on which, this paper also give timing simulation and static timing analysis results. Finally, byte file is given and downloaded into FPGA and tested.