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Soi Electrical Properties Testing And Low Power Soi Dram Design

Posted on:2003-01-29Degree:MasterType:Thesis
Country:ChinaCandidate:C L LiFull Text:PDF
GTID:2208360092981715Subject:Microelectronics and Solid State Electronics
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Silicon on Insulator (SOI) Technology was originally invented for the niche of radiation-hard circuits. High speed, low voltage and radiation-hardness are mam three advantages presented by SOI over bulk. Since the cost to produce SOI materials was high in the past, the application of SOI materials was limited in military industry and aerospace. More recently, the advent of new SOI wafer fabrication techniques and the explosive growth of portable microelectronic devices have attracted considerable attention on SOI for the fabrication of low-power (LP), low-voltage (LV), and high-frequency (HF) CMOS circuits.In this thesis, we study the electrical characterization on SOI wafers and design a low-power SOI CMOS DRAM structure.The electrical parameters of buried oxide and interface state in SOI structures influence the performance, reliability and the radiation hardness of devices fabricated in the superficial silicon film. Based on the experimental results and theory analysis, the characteristics of SOI wafers were discussed through using three different electrical characterization models: MOS, SIS, and MOSOS. SIMOX SOI wafers produced by ion implant processes were used in this experiment. The results for SIMOX SOI samples we got here revealed that all the three structures are valuable for SOI electrical characterization and SIS structure has irrefragable advantage over the other two structures.The SOI transistors have been the key devices for achieving the low voltage operation and low power consumption, because of the small junction capacitance, the small S-factor, and the small substrate bias effect. In our work, the stressless DRAM array has been newly developed for the lower voltage operation. In addition to the DRAM array, the logic circuitry with the body-bias-controlled SOI transistors has been developed for high-speed operation. Combine some new techniques for power reduction and our DRAM array, we design a new low-power SOI CMOS DRAM structure and study the performance of our circuits. The results we got in the simulation and test are valuable.mAbstractOur Thesis was supported by Project of Knowledge Innovation Program of the Chinese Academy of Sciences and AM fund of Shanghai 1C Design Center and AM Inc. USA.
Keywords/Search Tags:Electrical
PDF Full Text Request
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