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Fast Simulation Of Integrated Circuits And Waveform Compression

Posted on:2014-02-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y LiuFull Text:PDF
GTID:2208330434970496Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapid increase of the signal frequency and the decrease of the feature size of VLSI, it brings new challenges to integrated circuit design and verification due to more and more nanometer effects. SPICE tools became part of the race to develop increasingly more complex circuits, and were required to match their simulation capabilities with rapidly advancing transistor manufacturing technology. Further integration and downscaling of electronic circuits created a need to simulate larger design blocks, as well as entire chips. This meant scaling up simulation capabilities from circuits with thousands of transistors to circuits with millions of transistorsAlong with feature sizes of MOS devices well into the nanometer regime, physics-based analytical models have become enormously complicated and computationally expensive. The effect is evident in Spice-level simulators where up to80%of the run time gets consumed doing model evaluations. The need for simulation throughput together with the availability of large resident memory has sparked a renewed interest in approximate table models. An efficient table modeling algorithms is proposed to further improve the accuracy and efficiency of existing table modeling methods. It uses optimized BSP (Binary Space Partitioning) tree structure to store and build device table data and adopts polynomial segmentation fitting for approximation, also simplifies the table dimensions. In comparison with the existing table modeling methods, the proposed algorithm can effectively solve the problem of continuity and monotonicity, with higher accuracy and less memory usage. Moreover, the computational cost of the proposed method is reduced remarkably.The simulation data increases drastically with the increasing scale of integrated circuit (IC). For a circuit with0.1Millions of nodes, the size of the simulation data can reach several Giga Bytes. In order to reduce the size of simulation data, an efficient compression method for analog waveforms is proposed in this paper. The proposed method treats the waveform data at each time step as a frame. A reference frame is chosen every ten to hundred steps. For the data frames between these reference frames, we predict the waveforms of the data frames based on the reference frame firstly. If the differences between the real waveforms and the predicted waveforms are lower than a tolerance, we use the predicted data to represent these waveforms and thus compress the waveform data. If the differences are larger than the tolerance, we store the differences to recovery the waveforms. An adaptive quantization scheme is proposed to compress the difference data and improve the accuracy. After quantization, the entropy coding method is used to encoding the data to further reduce the size of the data. The proposed compression method can achieve high compression ratio while guaranteeing the accuracy. Furthermore, the computational cost of the proposed method is remarkably lower and it can handle mass data efficiently. The buffering requirement is remarkably lower. The simulation data can be compressed during the simulation. Experimental results demonstrate that the compression ratio by the proposed method can achieve9%with0.1%error.
Keywords/Search Tags:table model, interpolation, simulation waveform, compression
PDF Full Text Request
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