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Integrated Circuit Manufacture Of Selective Silicon Germanium Epitaxial Process

Posted on:2012-10-17Degree:MasterType:Thesis
Country:ChinaCandidate:H J TuFull Text:PDF
GTID:2208330335997803Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
According Moore's law:CMOS gate length will reduce thirty percent every eighteen months, the integration level will double, and production cost performance will double. In advanced CMOS, it can not fit device performance requirement only by shrink gate oxide thickness, so people have to find other way to improve device performance, such as high-K metal gate material application and stress enhancement technology. The important way for stress enhancement is use selective epitaxy silicon germanium replace silicon in PMOS source/drain area. Because germanium atom radius is larger than silicon, when germanium diffuses into silicon, PMOS source/drain area will have tensile stress. For channel, it has to suffer compress stress. When hole move in the channel with compress stress, its mobility will enhancement, so can improve device performance.In this thesis first introduces the growth theory and hardware structure of selective epitaxy silicon germanium process, how to characterize silicon germanium film and how to monitor it. The characteristic way including particle size, haze performance, SiGe thickness & Ge concentration, stacking fault and so on. It is very important for process which how to control selective epitaxy SiGe quality.Secondly, this thesis study the loading effect when grow selective epitaxy SiGe, include macro loading effect & micro loading effect. According research, for macro loading effect, with increase silicon transmission ratio, SiGe growth ratio and Ge concentration will reduce. Micro loading effect means within same wafer or same die, micro area with different silicon transmission ratio, cause SiGe THK & Ge% difference. This thesis analysis loading effect to poly through pitches effect, and introduces some ways about how to reduce loading effect.This thesis also study the effect factors when growth selective epitaxy SiGe, include temperature, chamber pressure, DCS(SiH2C12) partial pressure, GeH4 partial pressure, HC1 partial pressure. Analysis above five factors to SiGe thickness & Ge% effect's sensivity. From the result shows, for effect SiGe thickness sequence are GeH4 partial pressure > chamber pressure> temperature> HC1 partial pressure> DCS partial pressure, among them, HCl partial pressure is negative direction. For effect Ge%, the sequence are chamber pressure> GeH4 partial pressure> DCS partial pressure> temperature> HCl partial pressure, among them, temperature & DCS partial pressure are negative direction.In last this thesis analysis the selective epitaxy SiGe seed layer growth. With gate length continue shrink, it require Ge concentration continue increase. On the other hand is adding boron in SiGe to reduce thermal budget. The two development direction depends on the SiGe seed layer quality. In this thesis analysis how to get uniform SiGe seed layer, the seed layer not only can reduce boron diffuse, it also can well connect SiGe:B bulk layer.
Keywords/Search Tags:selective epitaxy, pattern loading effect, seed layer
PDF Full Text Request
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