Thin Epitaxy Process Design And Implementation For 8 Inch Silicon Wafer

Material of silicon epitaxial wafer has been the basic functional material of the current large-scale integrated circuits and other semiconductor silicon devices, which directly support the development of the electronic information technology industry. Thin silicon epitaxial wafers carry the important circuit function among semiconductor devices. N/N+ silicon epitaxial wafers have mainly been used in VLSI and discrete devices. At present,8 inch integrated circuit has a large share in the total output of China's integrated circuit. While the domestic 8 inch silicon epitaxial material, either production capacity or quality, can't meet the growing market demand in China. At the same time, with the increase of polishing wafer size,the uniformity of resistivity and thickness, as key parameters for epitaxial layer on N type high concentration substrate is more and more difficult to control. So there is practical significance for process design to improve the uniformity of parameters for 8 inch thin layer silicon.In this thesis, the growth characteristics and technological basis of silicon epitaxy are introduced, a series of studies on the application of 8 inch thin epitaxial layer are carried out, key factors which affect the resistivity uniformity, and thickness uniformity and crystal quality of epitaxial wafers are studied. The effect of silicon source flow rate and process temperature on the growth rate of different position in the silicon wafer was analyzed by design of different experiments. Test data show that the uneven thermal field distribution of silicon wafer is a main factor leading to the uneven thickness of N/N+ silicon epitaxial wafer. The process design of temperature compensation and flow distribution has been used to improve the uniformity of thermal field. The thickness uniformity of 8 inch N/N+ silicon epitaxial wafer is improved, and controlled within 0.8%. The main factor for the uneven resistivity of N/N+silicon epitaxial wafer is the gas phase self-doping phenomenon and solid diffusion of the polishing wafer impurity. In this thesis, we designed an improved polishing wafer, used high temperature processing method intrinsic growth method and two-step growth method and so on, all these can effectively restrain the self-doping and solid diffusion effects, make thin silicon epitaxial layer resistivity curve steep, meanwhile the resistivity uniformity of 8 inch N/N+ silicon epitaxial wafer is improved, and controlled within 2%.8 inch epitaxial materials produced by these methods have been used and verified in semiconductor integrated circuits and other semiconductor devices in our country, which promote the localization process of the key materials.