Passivation Layer On The Electrical Parameters Of Power Devices, Chip Simulation And Process Optimization

Passivation is an essential method to enhance the performance and liability of devices, which is also the key point of silicon process, the importance of passivation is very more prominent as MOS technique in high voltage IC and power integrated circuits.The application of LPCVD-deposited SIPOS film as a surface passivat in the fabrication of bipolar power transistors can effectively improve leakage current of devices and enhance their stability. In practice, however, it has been found that SIPOS film directly on the surface of the active area of devices will significantly affect their small current gain and BVceo characteristic. The small current gain of devices with their surface passivated using SIPOS+TEOS films can decrease by an average of 30% and even up to a maximum of 50% after reliability tests such as high temperature storage; the value of K will reduce 20% on average. The small current gain of devices can be improved by employing SIPOS+SiO_xN_y film, but such improvement is largely eclipsed by the occurrence of severe negative resistance which damages yields greatly.The thesis seeks to solve the problems in the current process through adjusting the deactivation layer structure, and confirms two new processes flow through experiment combining with the equipments could be used in the production, the two new processes are: 1. To replace the previous SIPOS+TEOS deactivation layer on the EB junction with silicon nitride layer using PECVD process, to replace the wet etching with dry etching, thus it has eliminated the hidden danger of drill etching on the film.2. To retain the oxide layer of Boron diffusion, eliminates the possibility of bringing in ion pollution in the process and the purity of oxide layer is guaranteed.There is no negative resistance phenomenon in the BVceo testing among the chips using the two new processes, and also we could control the small current changing under 6% in average through 168-hour's high temperature testing after sealing and the average changing rate of K value which is improved prominently under 3%. The secondary process has been applied to the production partially and been expanded from the experiment type of chip to other 2-3 types of chip. we have gained the customers' approval after the chips being transmitted to the customers for trial.